Oliver Schmidt
2020-05-06 17:04:36 UTC
Hi,
I've read quite a bit on this topic but I'm still sort of puzzled. So
I'd appreciate guidance.
So I want to code for a slot card with I/O addresses in the usual
$C0sn space. Mere read accesses to the I/O addresses already perform
actions so I need to be in control of all types of accesses to the I/O
addresses.
I want my code to be slot independent so the classic, naive would be
LDA $C080,x
STA $C080,x
The LDA $C080,x is without page-crossing so it's 4 cycles with a
single read :-) but the STA $C080,x is 5 cycles with a read before the
write :-(
The workaround I know of (from the Slinky RAM firmware) is
LDA $BFFF,x
STA $BFFF,x
The LDA $BFFF,x isn't necessary but one doesn't want to deal with two
different indexes. So the LDA $BFFF,x is with page-crossing meaning
it's 5 cycles with a read at page $BF :-) and the STA $BFFF,x is again
5 cycles with a read at page $BF :-)
This was for the 6502. My understanding is that the 65C02 does (just
like the 6502) a phantom read on the 5 cycle variants, but it happens
at the PC so it isn't relevant.
Where I'm rather unsure is the 65816. Does it really behave exactly
like the 6502 with regards to operations mentioned so far?
My code makes use of 65C02 specific instructions so I don't have to
care about the 6502 phantom reads. But I (of course) want my code to
run on the IIgs so my actual questions are:
1. Are my assumptions so far correct?
2. Do I really need a workaround in my scenario for the phantom reads
because of the 65816?
3. Is there another (ideally preferable) workaround beside the $BFFF
approach for my scenario? I don't consider self-modifying code to
avoid indexed addressing as a valid solution.
Thanks in advance,
Oliver
I've read quite a bit on this topic but I'm still sort of puzzled. So
I'd appreciate guidance.
So I want to code for a slot card with I/O addresses in the usual
$C0sn space. Mere read accesses to the I/O addresses already perform
actions so I need to be in control of all types of accesses to the I/O
addresses.
I want my code to be slot independent so the classic, naive would be
LDA $C080,x
STA $C080,x
The LDA $C080,x is without page-crossing so it's 4 cycles with a
single read :-) but the STA $C080,x is 5 cycles with a read before the
write :-(
The workaround I know of (from the Slinky RAM firmware) is
LDA $BFFF,x
STA $BFFF,x
The LDA $BFFF,x isn't necessary but one doesn't want to deal with two
different indexes. So the LDA $BFFF,x is with page-crossing meaning
it's 5 cycles with a read at page $BF :-) and the STA $BFFF,x is again
5 cycles with a read at page $BF :-)
This was for the 6502. My understanding is that the 65C02 does (just
like the 6502) a phantom read on the 5 cycle variants, but it happens
at the PC so it isn't relevant.
Where I'm rather unsure is the 65816. Does it really behave exactly
like the 6502 with regards to operations mentioned so far?
My code makes use of 65C02 specific instructions so I don't have to
care about the 6502 phantom reads. But I (of course) want my code to
run on the IIgs so my actual questions are:
1. Are my assumptions so far correct?
2. Do I really need a workaround in my scenario for the phantom reads
because of the 65816?
3. Is there another (ideally preferable) workaround beside the $BFFF
approach for my scenario? I don't consider self-modifying code to
avoid indexed addressing as a valid solution.
Thanks in advance,
Oliver